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TLE7242-2G 4 channel fixed frequen cy constant current control ic data sheet, rev. 1.0, july 2008 automotive power
data sheet 2 rev. 1.0, 2008-07-09 TLE7242-2G table of contents table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.3 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.3.1 on / off mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.3.2 constant current mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1 pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.2 pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4 general product characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.1 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.2 functional range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.3 thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5 functional description and electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1 supply and reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.2 input / output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.3 diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.3.1 on-state diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.3.2 off-state diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.4 output driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.5 current control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.6 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.6.1 spi signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.6.2 spi message structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.6.2.1 spi message #0 - ic version / manu facturer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.6.2.2 spi message #1 - main period set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.6.2.3 spi message #2 - pwm offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.6.2.4 spi message #3 - current set point and dither amplitude set . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.6.2.5 spi message #4 - dither period set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.6.2.6 spi message #5 - control variable set (kp and ki) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.6.2.7 spi message #6 - dynamic threshold value set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.6.2.8 spi message #7 - on/off control and fault mask configuration . . . . . . . . . . . . . . . . . . . . . . . . 38 5.6.2.9 spi message #8 - diagnostic configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5.6.2.10 spi message #9 - diagnostic read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5.6.2.11 spi message #10 - current read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 5.6.2.12 spi message #11 - autozero read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5.6.2.13 spi message #12 - duty cycle read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 6 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6.1 further application informat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 7 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 8 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table of contents
pg-dso-28-26 type package marking TLE7242-2G pg-dso-28-26 TLE7242-2G data sheet 3 rev. 1.0, 2008-07-09 4 channel fixed frequency constant current control ic TLE7242-2G 1overview 1.1 features ? low side constant current control pre-driver integrated circuit ? four independent channels ? output current programmable with 11 bit resolution ? current range = 0 to 1.2a (typ) with a 0.2 ? sense resistor ? resolution = 0.78125 ma/bit (typ) with a 0.2 ? sense resistor ? +/- 2% full scale error over temperature when autozero is used ? programmable pwm frequency via spi from approximately 50 hz to 4 khz (typ) ? programmable kp and ki coefficients for the pi controller for each channel ? programmable transient mode of operation to reduce settling time when large changes in the current set point are commanded. ? programmable superimposed dither. ? dither programmed by setting a dither step size a nd the number of pwm periods in each dither period ? programmed via the spi interface ? the dither for each channel can be enabled and programmed independently ? programmable synchronization of the pwm control signals. ? phase delay time set via the spi interface ? synchronization initiated via si gnal at the phase_sync input pin. ? channels within one device and between multiple devices can be synchronized. ? each channel can be configured to function as a simple on/off predriver or a constant current predriver via spi ? interface and control ? 32 bit spi (serial peripheral interface) - slave only ? enable pin to disable all channels or freeze all channels ? active low reset_b pin resets in ternal registers to their default state and disables all channels. ? open drain fault pin can be programmed to transition low when various faults are detected. ? 5.0v and 3.3v logic compatible i/o ? protection ? over current shutdown - monitored at posx pin. ? programmable over current threshold ? programmable over current delay time ? programmable over current retry time ? battery pin (bat) overvoltage shutdown. ? diagnostics ? over current
TLE7242-2G overview data sheet 4 rev. 1.0, 2008-07-09 ? open load in on state ? open load in off state ? short to ground ? test complete bit - indicates that fault detection test has completed ? control loop monitor capabilities ? the average current measurement over the last comp leted pwm cycle of each channel can be accessed via spi. ? the pwm duty cycle of each channel can be accessed via spi ? the auto zero values used to null the offset s of the input amplifiers can be accessed via spi ? required external components: ? n-channel logic level (5v) mosfet transistor with typical ron 100 m ? (e.g. bso604ns2) ? recirculation diode (ultrafast) ? sense resistor (0.2 ? for 1.2a average output current range) ? green product (rohs compliant) ? aec qualified 1.2 applications ? variable force solenoids (e.g. automatic transmission solenoids) ? other constant current solenoids ? idle air control ? exhaust gas recirculation ? vapor management valve ? suspension control 1.3 general description the tle7242 2g ic is a four channel low-side constant current control predriver ic. each channel can be configured to function either in on/off mode or in cons tant current mode by setting the appropriate mode bit in spi message #7. 1.3.1 on / off mode operation for on/off operation, the posx and negx pins must be co nnected to the circuit in ei ther of the configurations shown in figure 1 . if the sense resistor is included, the load current can be monitored by the microcontroller via a spi command. the open load in on state fault detection feature is disabled in on/off mode. note: an external flyback clamp is required in th is configuration otherwise the ic may be damaged.
data sheet 5 rev. 1.0, 2008-07-09 TLE7242-2G overview figure 1 external circuit diagram for on/off mode operation 1.3.2 constant current mode operation during constant current operation, the posx and negx pins must be connected to the circuit in the configuration shown in figure 2 . note: an external recirculation diode is required in this configuration otherwise the ic may be damaged. figure 2 external circuit diagram for constant current mode operation the constant current control circuit can operate in two modes; steady state mode and transient mode. steady-state mode during steady-state operation, the pwm control signal dr iven at the outx pin is co ntrolled by the control loop shown in figure 3 . the pwm frequency is programmed via the spi me ssage # 1. in this message the main period divider, n, can be set to any value between 79 and 2 14 -1. the equation for calculating the pwm frequency is: solenoid r sense posx negx outx posx negx outx r g r g q drv q drv solenoid c esd c esd v bat v bat posx negx outx solenoid r sense d recirc q drv c esd v bat r g n f f clk pwm * 32 =
TLE7242-2G overview data sheet 6 rev. 1.0, 2008-07-09 the 11 bit current set point is programmed via the sp i message #3. the equation for calculating the current setpoint is: the proportional coefficient (kp) and the integral coef ficient (ki) of the control loop are programmed in spi message #5. the kp and ki values should be set to values that result in the desired transient response of the control loop. the duty cycle of the outx pin can be calculated from the difference equations: where error is the differen ce between the commanded average current and measured average current in units of amps. where k indicates the integral number of pwm periods t hat have elapsed since current regulation was initiated. figure 3 control loop - steady-state mode auto zero when a channel is configured for constant current operat ion and the current set point is 000h for 256 consecutive pwm periods, an autozero sequ ence is initiated. the au tozero sequence will measure the offset of the current sense setpoint r (11bit) t setpoin ma current 320 2 ] [ 11 ? = () () () ) 1 ( 1 * 28 . 1 ) ( ) ( 1 * 28 . 1 ? + ? ? ? = + ? ? ? = k int k error n rsense ki k int k int k error n rsense kp k dutycycle a/d average autozero value ?on? - current set point dither step size dither generation + + + kp ki pwm block pwm clk + + dither steps outx posx negx amp + - auto zero autozero value ?off? duty cycle current read pre- load italics = can be monitored via spi underlined = can be programmed via spi
data sheet 7 rev. 1.0, 2008-07-09 TLE7242-2G overview measurement amplifiers. if th e autozero function is enabled in spi message #7, then the measured offset will be subtracted from the a/d converter output as shown in figure 3 when the current set point is greater than 0. dither a triangular dither waveform can be superimposed on the current set point by setting the dither enable bit in spi message #3. the amplitude and frequency of the dither waveform are programmed for each channel via spi messages #3 and #4. see the spi message section for details. the first programmed value is the step size of the dither waveform which is the number of bits added or subtracted from the setpoint per pwm period. one lsb of the dither step size is 1/16 the magnitude of the nominal setpoint current value. the second programmed value is the number of steps in one quarter of the dither waveform. when dither is enabled, a new average current set poin t will not be activated until the current dither cycle has completed. the dither cycle is comple ted on the positive zero crossing of the dither waveform. a new dither amplitude setting, a new dither frequency setting, or a dither disable command will also not be activated until the current dither cycle has completed see figure 4 . figure 4 new dither values programmed and the resultant waveform timing note: the actual dither waveform is attenuated and phas e shifted according to the frequency response of the control loop. if a channel enters transien t mode operation while the di ther waveform is active, the dither wave-form will pause until transient mode is exited. transient mode when a large change in the current set point occurs, the device can be programmed to enter transient mode of operation. the setpoint change threshold required to initiate transient mode can be programmed in spi message #6. the purpose of this mode of operation is to reduce the transition time of the load current after a large change in setpoint. in this mode of operation the outx pin signal is controlled by the state machine shown in figure 5 . the control method in this mode is similar to hysteretic control, the outx signal transitions high or low based on the immediate value of the measured output current. the pwm frequency is not fixed in this mode of operation. the device will automatically switch from trans ient mode of operation to st eady state operation at the start of the first pwm period after the new set point has been reached. pwm_start dither dither parameter change
TLE7242-2G overview data sheet 8 rev. 1.0, 2008-07-09 figure 5 transient mode state diagram a typical current waveform during transient mode operation is shown in figure 6 . starting from a set point i, the new set point ii is accepted a short time after the ri sing edge on cs_b. the outx pin remains high until the measured load current has reached the new set point. the outx pin is then toggled on and off to maintain the load current near the new set point un til the next pwm period begins. the device will then switch back to steady state control and the outx pin will be co ntrolled by the cont rol loop shown in figure 3 . during the transition from transient mode operation to st eady state operation, the int egrator is pre-loaded with a spi programmable value. this value should be chosen to give an initial pwm duty cycle approximately equal to the duty cycle required to regulate the load current at the new set point. figure 6 transient mode timing diagram steady- state mode reset outx = high outx = low outx = high leave hyst mode outx := low controller := stop calc dc outx := low controller := stop set point change > threshold new set point > old set point set point change > threshold new set point < old set point measured current > new set point measured current < new set point measured current < new set point measured current > new set point outx = low start of pwm period start of pwm period next adc value int preload outx := low controller := stop pwm i l setpoint ? setpoint t spi cs_b setpoint ? accepted steady state mode begins transient mode begins
data sheet 9 rev. 1.0, 2008-07-09 TLE7242-2G block diagram 2 block diagram figure 7 block diagram pos0 out0 neg0 pos1 out1 neg1 pos2 out2 neg2 pos3 out3 neg3 spi interface sck si so cs_b fault reset_b bat phase_sync v5d v5a gnd_d gnd_a clk enable v_signal test supply biasing monitoring logic v_signal v_signal current control block diagnostics v5d current control block diagnostics v5d current control block diagnostics v5d current control block diagnostics v5d
TLE7242-2G pin configuration data sheet 10 rev. 1.0, 2008-07-09 3 pin configuration 3.1 pin assignment figure 8 pin configuration 3.2 pin definitions and functions pin symbol i/o analog /digital function 1 out3 o a gate driver output for channel #3. connect to the gate of the external mosfet. 2 out2 o a gate driver output for channel #2. connect to the gate of the external mosfet. 3 pos3 i a channel #3 positive sense pin. connect to the "load" side of the external sense resistor. 4 neg3 i a channel #3 negativ e sense pin. connect to the "fet" side of the external sense resistor. 5 neg2 i a channel #2 negativ e sense pin. connect to the "fet" side of the external sense resistor. 6 pos2 i a channel #2 positive sense pin. connect to the "load" side of the external sense resistor. 7 gnd_a - - analog ground 8 v5a - - 5v supply pin for analog. an exte rnal capacitor is to be connected between this pin and gnd_a near this pin. 9 pos1 i a channel #1 positive sense pin. connect to the "load" side of the external sense resistor. tle7242 2g out 3 out 2 neg 3 pos 3 fault reset_b cs_b enable neg 2 pos 2 v5a gnd_a sck v5d gnd_d clk so v_signal test si phase_sync bat neg 1 pos 1 neg 0 pos 0 out 1 out 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15
data sheet 11 rev. 1.0, 2008-07-09 TLE7242-2G pin configuration 10 neg1 i a channel #1 negativ e sense pin. connect to the "fet" side of the external sense resistor. 11 neg0 i a channel #0 negativ e sense pin. connect to the "fet" side of the external sense resistor. 12 pos0 i a channel #0 positive sense pin. connect to the "load" side of the external sense resistor. 13 out1 o a gate driver output for channel #1. connect to the gate of the external mosfet. 14 out0 o a gate driver output for channel #0. connect to the gate of the external mosfet. 15 bat i a battery sense input for over vo ltage detection. connect through a series resistor (e.g. 1 kohm) to the solenoid supply voltage. a large electrolytic capacitor (e.g. 47uf) should be placed between the bat supply and ground. 16 phase_sync i d used to synchronize the ri sing edges of the pw m signal on the outx pins for each channel. 17 test i d used for ic test. must be connected to gnd_d for specified operation of the ic. 18 si i d spi serial data in 19 v_signal i - supply pin for the spi so output and the pull-ups of the digital inputs cs_b and reset_b. an ex ternal capacito r must be con- nected between this pin and gnd_d near this pin. 20 so o d spi serial data out 21 gnd_d - - gnd pin for digital and driver circuitry. 22 clk i d main clock input for the ic. a clock input of 20 mhz to 40 mhz is required. 23 v5d - - 5v supply pin for the digital ci rcuit blocks and the out pin driver circuits. a pair of external capaci tors is to be connected between this pin and gnd_d very near th is pin. example values of the external capacitors are 100nf and 100pf. 24 sck i d spi clock input 25 cs_b i d spi chip select bar (low active signal) 26 enable i d when this input pin is low all channels are turned off (zero current) or remain in their last state, depending on how the channel is programmed to respond 27 reset_b i d when this input pin is low all channels are tu rned off and all internal registers are reset to thei r default state. the part must be held in reset by an external source until all supplies are stable and within tolerance. 28 fault o d this open drain output pin is pulled low when a fault condition is detected. certain faults can be masked via spi. pin symbol i/o analog /digital function
TLE7242-2G general product characteristics data sheet 12 rev. 1.0, 2008-07-09 4 general product characteristics 4.1 maximum ratings note: stresses above the ones listed here may cause perm anent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note: integrated protection functions are designed to prevent ic destruction under fault conditions described in the data sheet. fault conditions are considered as ?outside? normal operating range. protection functions are not designed for continuous repetitive operation. absolute maximum ratings 1) t j = -40 c to +150 c; all voltages with respect to ground, posit ive current flowing into pin (unless otherwise specified) 1) not subject to production test, specified by design. pos. parameter symbol limit values unit conditions min. max. voltages 4.1.1 battery input (vbat) v bat -13 50 v ? 4.1.2 supply voltage (logic) v 5d, v 5a, v signal -0.3 6.0 v ? 4.1.3 posx, negx v pos, v neg -0.3 50 v ? 4.1.4 posx-negx v pos- v neg -0.2 13 v ? 4.1.5 outx v out -0.3 min(v 5d + 0.3; 6) v? 4.1.6 reset_b, si, sck, cs_b, clk, test, phase_sync, enable v io -0.3 min(v 5d + 0.3; 6) v? 4.1.7 so, fault v io -0.3 min(v signal + 0.3; 6) v? 4.1.8 maximum difference between v5d and v5a -500 500 mv ? currents 4.1.9 input clamp current i clamp 5?5ma? temperatures 4.1.10 storage temperature t stg -65 150 c? 4.1.11 junction temperature t j -40 150 c? esd susceptibility 4.1.12 hbm ? -2 2 kv 2) 2) esd susceptability hbm accord ing to eia/jesd 22-a 114b 4.1.13 cdm all pins ? -500 500 v 3) 3) esd susceptability cdm according to eia/jesd22-c101 4.1.14 cdm corner pins ? -750 750 v 3)
data sheet 13 rev. 1.0, 2008-07-09 TLE7242-2G general product characteristics 4.2 functional range t j = -40 c to +150 c; all voltages with respect to ground, posit ive current flowing into pin (unless otherwise specified) note: within the functional range the ic operates as de scribed in the circuit description. the electrical characteristics are specifi ed within the conditions given in the re lated electrical ch aracteristics table. 4.3 thermal resistance t j = -40 c to +150 c; all voltages with respect to ground, posit ive current flowing into pin (unless otherwise specified) pos. parameter symbol limit values unit conditions min. max. 4.2.1 supply voltage (vbat) - full parametric operation on all functions except fet pre-drivers v bat 5.5 42 v ? 4.2.2 supply voltage (v5d) v v5d 4.75 5.25 v ? 4.2.3 supply voltage (v5a) v v5a 4.75 5.25 v ? 4.2.4 v_signal v v_signal 3.0 5.25 v ? 4.2.5 clock frequency f clk 20 40 mhz 4.2.6 pwm frequency f pwm 50 4000 hz 4.2.7 common mode voltage on posx, negx pins v pos , v neg ?42v? pos. parameter symbol limit values unit conditions min. typ. max. 4.3.1 junction to ambient r thja ?50?k/w 1) 1) specified r thja value according to natural convestion on fr4 2s0p board; the product (chip + package) was simulated on a 60.0 x 45.0 x1.5 mm board (2 x 70um).
TLE7242-2G functional description and electrical characteristics data sheet 14 rev. 1.0, 2008-07-09 5 functional description an d electrical characteristics note: the listed characteristics are ensured over the operating range of the integrated circuit. typical characteristics specify mean va lues expected over the production sp read. if not otherwise specified, typical characteristics apply at t a = 25 o c and the given supply voltage. 5.1 supply and reference the device includes a power- on reset circuit. this featur e will disable the channels and re set the intern al registers to their default values when the vo ltage on v5a and/or v5d are below their respective reset thresholds. the v5d pin and gnd_d pin are the supply and ground pins for the digital circuit blocks and the outx pin driver circuits. the current through these pi ns contain high frequency componen ts. decoupling with ceramic capacitors and careful pcb layout are required to obtain good emc performance. the v5a pin and gnd_a pin are the supply and ground pins for the analog circuit blocks. the v_signal pin supplies the spi output pin (so) and is the source voltage for the pull up currents on the cs_b and reset_b pins. v_signal should be connected to th e i/o supply of the microcontroller (3.3v or 5.0v). the bat pin is an input pin used to detect over voltage fa ults. this pin is not a power supply input. a series resistor should be connected between this pin and the so lenoid supply voltage for transient protection. electrical characteristics: v5d = 4.75v to 5.25v, vbat = 5.5v to 42v, t j = -40 c to +150 c, all voltages with resp ect to ground, positive current flowing into pin (unless otherwise specified) pos. parameter symbol limi t values unit conditions min. typ. max. 5.1.1 undervoltage reset (internally triggered) v v5a 3.5 ? 4.5 v internal reset occurs if v5a is under the undervoltage limit 5.1.2 undervoltage reset (internally triggered) v v5d 1.0 ? 4.5 v internal reset occurs if v5d is under the undervoltage limit 5.1.3 v5d supply current i v5d ??30 50 ma ma f clk =20mhz f clk =40mhz 5.1.4 v5a supply current i v5a ??25ma 5.1.5 v_signal supply current i v_signal ? ? 1.0 ma so pin in hi-z state, digital inputs in default state 5.1.6 vbat current i vbat ? ? 150 50 5 a a a full operating range v5a=5v, bat=14v 1) v5a=0v, bat=14v 1) 1) not subject to production test, specified by design.
data sheet 15 rev. 1.0, 2008-07-09 TLE7242-2G functional description and electrical characteristics 5.2 input / output all digital inputs are compatible with 3.3 v and 5 v i/o l ogic levels. the supply voltage for the spi output so is the v_signal pin. all digital inputs are pulled to a known stat e by a weak internal current source or current sink when not connected. however, unused digital input pins should be connected to ground or to v_signal (according to the desired functionality) by an external connection or resistor. all input pi n weak internal current sources are supplied by the v_signal pin. the reset_b pin is an active low input pin. when this pi n is low, all channels are off, and all internal registers are reset to their default states. the device must be held in reset by an external source until all the power supplies have stabilized. the ic contains an internal power on and undervoltage reset which becomes active when v5d or v5a fall below the undervoltage reset threshold (vuva, vuvd). the enable pin is an active high input pin which must be held high for normal operation of the device. when this pin is held low all channels are eit her turned off or will remain in the last state, depending on how the enable behavior of the channel is programmed via spi. the default condition is that all channe ls are turned off when the enable pin is low. the clk pin is the main clock input for the device. the in put thresholds are compatible with 3.3 v and 5.0 v logic levels. no synchronization is required between the clock signal connected to the clk pin and the spi clock signal (sck). all frequencies of operation (pwm signals, a/d samp ling, diagnostics, etc.) are based on this clock input. also, this clock is required in order for the de vice to accept and respond to spi messages. figure 9 clk timing diagram the phase_sync pin is an input pin th at can be used by the microcontro ller to synchronize the pwm control signals of multiple channels. the desired phase delay between the rising edge of the signal applied to the phase_sync pin and the rising edge of the pwm signal of each channel can be programmed independently via spi message #2. the equation fo r calculating the offset is: each time the phase sequence occurs, the ic will latch a bit which is reported via the response to spi message #11. (see spi interface section for bit/message location.) this latch is cleared when the message is read. note: the pwm periods are restarted wh en a rising edge is detected on the phase_sync pin. a periodic pulse train on this pin will dist urb the current regulation. clk t 14 1/f clk t 15 vih min vil max pwm offset f offset phasesynch t * 32 =
TLE7242-2G functional description and electrical characteristics data sheet 16 rev. 1.0, 2008-07-09 figure 10 phase synchronization diagram the test pin is an input pin that is used during ic level test. this pin should be connected directly to ground for normal device operation. the fault pin is an open drai n output pin. this pin will be pulled low by the device when an unmasked fault has been detected. the fault masks are programmed via spi message #7. electrical characteristics: v5d = 4.75v to 5.25v, vbat = 5.5v to 42v, t j = -40 c to +150 c, all voltages with resp ect to ground, positive current flowing into pin (unless otherwise specified) 5.3 diagnostics the tle7242 2g includes both on-state and off-state dia gnostics. on-state diagnosti cs are active when the outx pin is driven high and off-state diag nostics are active when the outx pin is driven low. a detected fault can be used to activate the open drain fault pin on the ic. this pin can be used to interrupt the microcontroller when a pos. parameter symbol limi t values unit conditions min. typ. max. 5.2.1 logic input low voltage v ilmax ??0.8v 5.2.2 logic input high voltage v ihmin 2.0 ? ? v 5.2.3 logic output low voltage v olmax ??0.2v i l =200 a 5.2.4 logic output high voltage v ohmin 0.8*v_ signal ??v i l =-200 a 5.2.5 pull down digital input (si, clk, sck, phase_sync, enable, test) i pd 10 ? 50 a v in =v_signal (current drain to ground) 5.2.6 pull up digital input (cs_b, reset_b) i pu -10 ? -50 a v in =0v (current drain from v_signal) 5.2.7 fault pin voltage v fault ? ? 0.4 v active state; i fault =2ma 5.2.8 clk high time (rise 2.0v to fall 2.0v) t 14 8??ns 5.2.9 clk low time (fall 0.8v to rise 0.8v) t 15 8??ns outx pwm/32 clk phase_sync t1 t1 gate turns off on-time cut short normal turn off time programmed delay = 8/32 pwm periods
data sheet 17 rev. 1.0, 2008-07-09 TLE7242-2G functional description and electrical characteristics fault is detected. certain faults can be prevented from activating the fault pin by setting the fault mask register in spi message #7. once a fault is detected it is latched into the fault register. the microcontroller can access the fault register by sending spi message #9. if the reset_b line transitions high-to-low , a rl bit is latched into the fault register. the re gister is cleared after it is read from the spi. the rl bit in the fault register will not be set again until the next high-to-low transition occurs on th e reset_b pin. if the enable pin voltage is low, the enl bit is latched in the fault register. the enl bit is cleared when the enable pin returns to a high state and the fa ult register is accessed by spi message #9. the diagnostic delay timers for the on-state and off-stat e diagnostic functions are derived from the master clock signal applied to the pin clk using a programmable prediv ider. this predivider is programmable by the dt1 and dt0 bits in spi message #7. three fault types in 4 different fault bits are defined: the fault bit is 1 if the fault is detected. note: in order to differentiate between a short to ground failure and an open load failure, the channel must be turned off (setpoint = 0ma). tested diagnostic bits the tested bits allow the distinction between a true no fa ult and a no fault due to an untested state (the detection interval has yet to occur). for instance when the calculated duty cycle is too low to complete th e short to battery test. table 1 timebase for diagnostics dt1 dt0 pre-divider tested timer and fault detection timer period. f clk =20 mhz f clk =40 mhz 0012864 sec 32 sec 0119296 sec 48 sec 1019296 sec 48 sec 1 1 256 128 sec 64 sec table 2 diagnostic flags / bits fault type abr. gate is on gate is off short to ground fault sg ol-on-f reported (=0 in on/off mode) bit sg-f short to battery fault sb bit sb-f open load fault ol bit ol-on-f (=0 in on/off mode) bit ol-off-f 10 9 * _ = fault clk fault period diag n f predivider n t
TLE7242-2G functional description and electrical characteristics data sheet 18 rev. 1.0, 2008-07-09 two fault tested bits are defined: the tested bit is set to 1 when the fault test has completed successfully. each fault type can be described by the two bits: fault and tested. figure 11 diagnostic block diagram table 3 diagnostics tested bits / flags tested type outx high outx low short to ground and open load off tested bit off-t short to battery tested bit sb-t table 4 fault vs. tested bits matrix and interpretation fault tested interpretation by microcontroller 0 0 this fault type has not been tested 0 1 no fault - the fault type has been tested and no fault is present 1 0 this combinatio n cannot occur 1 1 fault - this particular fault type has occurred predivider 1:128 1:192 1:256 tested timer 1..10 (shared) digital filter open load off (only while off) digital filter short to ground (only while off) digital filter short to battery (only while on) gate on counter 1..64 fault filter timer (1..10) (shared) v pos v ol v pos v sg v pos v sb ol-fa sg-fa sb-fa pwm mode enabled pwm start clear logic divider select (spi register) masterclock ol-off-fd sg-fd sb-fd ol-on-f ol-off-f (open load off fault) sg-f (short to ground fault) sb-f (short to battery fault) ol-on-f (open load on fault) off-t (short to ground and open load off tested) sb-t (short to battery tested) read spi fault register gate is on clear clear clear
data sheet 19 rev. 1.0, 2008-07-09 TLE7242-2G functional description and electrical characteristics 5.3.1 on-state diagnostics when the outx pin transitions high, t he fault timers are cleared to 0 and th e tested timer starts. if the tested timer expires, the bit sb-t (in the spi register #9) is set to 1. if the outx pin tr ansitions low, the tested timer is cleared and then used for the off-state diagnostics. if the analog sb fault signal (sb-fa) changes to 1, the fault filter timer starts. if the fault filter timer expires, the digitally filtered sb fault signal (sb-fd) is set to one. if sb-fa changes to 0, sb-fd changes immediately to 0 and the filter timer is cleared to 0. a sb-fd=1 and sb-t=1 switches off the outx signal and the sb-f bit in the fault register will be set. the outx pin remains in the off state until the fault retry pwm period counter expires. if the spi fault register is read, then the sb-f bit and th e sb-ft bit in the fault register are cleared. also, the tested timer is cleared to 0. the short to battery (sb) detection functions in both on/off and constant current mode. the sg-fd and ol-off- fd signals are held to 0 while the outx pin is high. if the tle7242 2g ic is in on/off mode, open l oad on detection is disabled (ol-on-f = 0). if the tle7242 2g ic is not in on/off mode and the ou tx pin is high for 64 pwm periods, then open load fault on mode is detected and the ol-on-f bi t in the fault register is set. th is bit will be cleared when a spi fault read occurs. if the outx pin remains in a high state, then th e open load - on fault condition is detected again after another 64 pwm cycles. figure 12 on-state diagnostic timing - short to vbat pwm_start outx vpos load current sb-t sb-f spi read addr 9 tested timer fault filter fault retry time (address #8) short to vbat load ok short vsb tested timer fault filter
TLE7242-2G functional description and electrical characteristics data sheet 20 rev. 1.0, 2008-07-09 figure 13 open - on 5.3.2 off-state diagnostics the off-state diagnostics function in both constant current mode and in on/off mode. when the outx pin transitions low, the fault timers are clea red to 0 and the tested timer starts to count up. if the tested timer expires, the bit off-t in th e fault register is set. if a spi fault register read occurs, the tested timer is cleared to 0 and starts again to count up. if the outx pin transitions high, th e tested-timer is cleared to zero and then used for on-state diagnostics. if the analog ol fault signal (ol-fa) changes to 1, the fault filter timer starts to count up. if the fault filter timer expires, the digitally filtered ol faul t signal (ol-on-fd) is set to one. if ol-fa changes to 0, ol-fd changes immediately to 0 and the fault filter timer is cleared to 0. if the analog sg fault signal (sg-fa) changes to 1, the faul t filter timer is cleared to 0 and starts to count up. if the fault filter timer expires, the digitally filtered sg fault signal (sg-fd) is set to one. if sg-fa changes to 0, sg-fd changes immediately to 0 and the fault filter timer is cleared to 0. if sg-fd = 1 and the tested timer is expired then the sg-f bit in the fault register is set and the ol-off-f bit in the fault register remains unchanged (independently from ol-off-fd). if sg-fd = 0 and ol-off-fd = 1 then the ol-f bit in the fault register is set. if a spi fault read occurs, the off-t bit, the sg-f bit an d the ol-f bit in the spi registers are cleared to zero (and the timers are cleared to 0). pwm_start outx vpos ol-on-f spi message diagnostic read 64 * pwm period
data sheet 21 rev. 1.0, 2008-07-09 TLE7242-2G functional description and electrical characteristics figure 14 off-state diagnostics figure 15 off-state diagnostics timing diagram - open negx outx posx v supply solenoid v5a (vol+vsg)/2 (2.5v) + - - + vol (3v) vsg (2v) + oa cmp cmp - digital filter digital filter ol-fa ol-off-fd sg-fa sg-fd tested timer (off) ol-off- fault sg- fault ipu(sg) (100ua) ipd(ol) (100ua) latch latch latch sg/ol-off tested cneg cpos v pos outx off-t ol-off-f spi message diagnostic read tested timer fault filter tested timer fault filter load ok open vol vsg
TLE7242-2G functional description and electrical characteristics data sheet 22 rev. 1.0, 2008-07-09 figure 16 off-state diagnostics ti ming diagram - short to ground over voltage shutdown and diagnostics if the voltage at the bat pin is above vbat ov , the output drivers set all outx pins to low, and a diagnostic bit is set (spi message +11 bit ovl). during over voltage condit ion the integrator of the st eady state current control is halted (actual value of the duty cycle is not changed during over voltage). all other func tions operate normally (e.g. adc, dithering, auto zero, filters, ?). electrical characteristics: v5d = 4.75v to 5.25v, vbat = 5.5v to 42v, t j = -40 c to +150 c, all voltages with resp ect to ground, positive current flowing into pin (unless otherwise specified) pos. parameter symbol limit values unit conditions min. typ. max. 5.3.1 over voltage shutdown v batov 42 ? ? v raise vbat until all outputs shut down 5.3.2 open load detection voltage v pos(ol) v5a-2.5 ? v5a-1.5 v 5.3.3 pos pin ol pull down current i pd(ol) 60 100 150 av5a=5v, v pos =v neg =v5a 5.3.4 short to gnd detection voltage v pos(shg) v5a-3.5 ? v5a-2.5 v 5.3.5 pos pin sg pull-up current i pd(shg) -60 -100 -150 av5a=5v, v pos =v neg =0v 5.3.6 neg bias current - low common mode i neg(l) -40 ? 10 av5a=5v, v pos =v neg =0v 5.3.7 neg bias current - high common mode i neg(h) 0?60 av5a=5v, v pos =v neg =v5a v pos outx off-t sg-f spi read addr 9 tested timer fault filter tested timer fault filter load ok short to ground vol vsg
data sheet 23 rev. 1.0, 2008-07-09 TLE7242-2G functional description and electrical characteristics 5.3.8 pos fault threshold voltage v flt 0.6 0.7 0.8 v pos voltage required to trigger a short to battery fault: config bits = 00 5.3.9 pos fault threshold voltage v flt 0.8 0.9 1.0 v pos voltage required to trigger a short to battery fault: config bits = 01 5.3.10 pos fault threshold voltage v flt 1.0 1.1 1.2 v pos voltage required to trigger a short to battery fault: config bits = 10 5.3.11 pos fault threshold voltage v flt 1.2 1.3 1.4 v pos voltage required to trigger a short to battery fault: config bits = 11 5.3.12 fault filter timer n fault 910clocks 5.3.13 fault filter time t ff clock divider (spi message 7) 00 - predivider 128 01, 10 - predivider 192 11 - predivider 256 5.3.14 tested timer time t tt clock divider (spi message 7) 00 - predivider 128 01, 10 - predivider 192 11 - predivider 25 6 v5d = 4.75v to 5.25v, vbat = 5.5v to 42v, t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin ( unless otherwise specified) pos. parameter symbol limit values unit conditions min. typ. max. clk fault f predivider n ? ?
TLE7242-2G functional description and electrical characteristics data sheet 24 rev. 1.0, 2008-07-09 5.4 output driver the outx pins of the device are connected to the gates of the external mosfet transistors. the outx pin driver circuits charge and discharge the mosfet gate capacitanc e with a constant current source and sink. the supply for the current source is the v5d pin. in ternal resistors to ground are included on the outx pins so that the external mosfet is held in the off state when power is not applied to the device. an external resistor is typically placed between the outx pin and the gate of the external mosfet in order to set the mosfet turn-on and turn-off times. the value of the re sistor must be chosen such that the turn-on and turn- off times of the mosfet are no longer than 1/(fpwm*32). electrical characteristics: v5d = 4.75v to 5.25v, vbat = 5.5v to 42v, t j = -40 c to +150 c, all voltages with resp ect to ground, positive current flowing into pin (unless otherwise specified) 5.5 current control electrical characteristics: v5d = 4.75v to 5.25v, vbat = 5.5v to 42v, t j = -40 c to +150 c, all voltages with resp ect to ground, positive current flowing into pin (unless otherwise specified) pos. parameter symbol limi t values unit conditions min. typ. max. 5.4.1 passive gate pull down resistance r pd 50 ? 200 k ? internal pull down resistor present at each outx pin 5.4.2 outx source current i o_src -15 ? -30 ma v out = v5d-2v 5.4.3 outx sink current i o_snk 15 ? 30 ma v out = 2v pos. parameter symbol limi t values unit conditions min. typ. max. 5.5.1 offset error output from average block in figure 3 . 1 count = 320/rsense * 2 -14 ma 0 ? 240 counts autozero disabled.vpos- vneg=0mv vpos, vneg 30v 5.5.2 gain error -2% ? 2% % autozero enabled.vpos- vneg=300mv vpos, vneg 30v
data sheet 25 rev. 1.0, 2008-07-09 TLE7242-2G functional description and electrical characteristics 5.6 serial peripheral interface (spi) spi messages for the tle7242 2g ic are 32-bit values broken down into the following fields. bit 31: read/write bit - 0 = read 1 = write bits 30-26: message identifier bits 25-24: channel number (00, 01, 10, 11) bits 23-0: message data the message from the microcontroller must be sent msb fi rst. the data from the so pin is sent msb first. the tle7242 2g will sample data fr om the si pin on the rising edge of sck and will shift data out of the so pin on the rising edge of sck. all spi messages must be exactly 32-bits long, otherwis e the spi message is discarded. the response to an invalid message (returned in the next spi message) is the message with identifier 00000 (manufacturer id). when the enable pin is low, all spi writes commands are executed as read commands. when reset_b pin is low, the spi po rt is disabled. no spi messages are received and no responses are sent. the so pin remains in a high impedance state. there is a one message delay in t he response to each message (i.e. th e response for message n will be returned during message n+1). read/write operation is referenced from the spi master. the tle7242 2g ic is the slave device. some messages, such as diagnostic in formation, do not use the channel numb er field. in these cases the channel number is not part of the response. when bit 31 is = 0 to denote a read operation to the ic, the message data in bits 23-0 of the sent message are ignored, but will contain valid da ta in the response message. all response data (either from a read or write operation) is the direct contents of the addressed internal register, and is not an echo of the data sent in the previous spi message. the response to the first spi message after a reset is message #0 (ic version / manufacturer).
TLE7242-2G functional description and electrical characteristics data sheet 26 rev. 1.0, 2008-07-09 5.6.1 spi signal description electrical characteristics: v5d = 4.75v to 5.25v, vbat = 5.5v to 42v, t j = -40 c to +150 c, all voltages with resp ect to ground, positive current flowing into pin (unless otherwise specified) pos. parameter symbol limi t values unit conditions min. typ. max. 5.6.1 t lead t 1 140 ? ? ns cs_b falling (0.8v) to sck rising (0.8v) 5.6.2 t lag t 2 50 ? ? ns sck falling (0.8v) to cs_b rising (0.8v) 5.6.3 t 3 450 ? ? ns cs_b rise (2.0v) to cs_b fall (2.0v) 5.6.4 1/f sck period of sck t 4 100 ? ? ns sck rise to rise 5.6.5 t 5 10 ? ? ns sck falling (0.8v) to cs_b fall (2.0v) 5.6.6 t 6 40 ? ? ns sck high time (rise 2.0v to fall 2.0v) 5.6.7 t 7 40 ? ? ns sck low time (fall 0.8v to rise 0.8v) 5.6.8 t 8 10 ? ? ns cs_b rise (2.0v) to sck rise (0.8v) 5.6.9 t su_si t 9 20 ? ? ns si setup time to sck rise (0.8v) 5.6.10 t hold_si t 10 20 ? ? ns si hold time after sck rise (2.0v) 5.6.11 t so_enable t 11 ? ? 110 ns cs_b fall (2.0v) to so bit0 valid 5.6.12 t valid t 12 ? ? 80 ns so data valid after sck rise (2.0v) 5.6.13 t so_disable t 13 ? ? 110 ns so tristate after cs_b rise (2.0v) 5.6.14 number of clock pulses while cs_b low 32 ? 32 5.6.15 so rise time t so_rise ? ? 50 ns (20% to 80%) 5.6.16 so fall time t so_fall ? ? 50 ns (80% to 20%) 5.6.17 input pin capacitance. cs_b, si, and sck c in ??20pf 5.6.18 so pin capacitance c so ??25pftristate
data sheet 27 rev. 1.0, 2008-07-09 TLE7242-2G functional description and electrical characteristics figure 17 spi timing diagram bit 3 1 msb bit 0 lsb don?t care don?t care clock 1 clock 2 clock 3 clock 31 clock 32 bit 3 0 bit 2 9 bit 1 don?t care lsb high impedance high impedance time time time time don?t care don?t care sck si so t 6 t 4 t 7 t 1 t 5 t 10 t 9 t 11 t 12 t 2 t 3 t 8 t 13 cs _b bit 3 1 msb bit 3 0 bit 2 9 bit 0 bit 1
TLE7242-2G functional description and electrical characteristics data sheet 28 rev. 1.0, 2008-07-09 5.6.2 spi message structure 5.6.2.1 spi message #0 - ic version / manufacturer sent values: ic version / manufacturer reset value: 00 c1 00 00 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r/w msg_id not used 1514131211109876543210 not used field bits type description r/w 31 read / write bit 0 = read 1 = write msg_id 30:26 message identifier 0 0000 = ic version / manufacturer response: ic version / manufacturer reset value: 00 c1 00 00 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0msg_id00 ic manuf id 1514131211109876543210 version number 00000000 field bits type description msg_id 30:26 message identifier 0 0000 = ic version / manufacturer ic manuf id 16:23 ic manufacturer id number 1100 0001= infineon technologies version number 8:15 version number 0000 0010 = k11
data sheet 29 rev. 1.0, 2008-07-09 TLE7242-2G functional description and electrical characteristics 5.6.2.2 spi message #1 - main period set sent values: main period set reset value: 00 00 02 71 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r/w msg_id ch1 ch0 unused 1514131211109876543210 not used pwm divider - n field bits type description r/w 31 read / write bit 0 = read 1 = write msg_id 30:26 message identifier 0 0001 = main period set channel 25:24 channel number n13:0 pwm divider n response: main period set reset value: 00 00 02 71 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 msg_id ch1ch000000000 1514131211109876543210 0 0 pwm divider - n field bits type description msg_id 30:26 message identifier 0 0001 = main period set channel 25:24 channel number n13:0 pwm divider n n f f clk pwm * 32 =
TLE7242-2G functional description and electrical characteristics data sheet 30 rev. 1.0, 2008-07-09 5.6.2.3 spi message #2 - pwm offset sent values: pwm offset reset value: 00 00 00 00 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r/w msg_id ch1 ch0 unused 1514131211109876543210 not used phase sync offset field bits type description r/w 31 read / write bit 0 = read 1 = write msg_id 30:26 message identifier 0 0010 = pwm offset channel 25:24 channel number phase synch 4:0 phase synch offset response: pwm offset reset value: 00 00 00 00 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 msg_id ch1ch000000000 1514131211109876543210 00000000000 phase sync offset field bits type description msg_id 30:26 message identifier 0 0010 = pwm offset channel 25:24 channel number phase synch 4:0 phase synch offset pwm offset f offset phasesynch t * 32 =
data sheet 31 rev. 1.0, 2008-07-09 TLE7242-2G functional description and electrical characteristics 5.6.2.4 spi message #3 - current set point and dither amplitude set dither sent values: current set point and dither amplitude set reset value: 00 00 00 00 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r/w msg_id ch1 ch0 en on/ off dither step size 1514131211109876543210 dither step size dither on/ off current set point field bits type description r/w 31 read / write bit 0 = read 1 = write msg_id 30:26 message identifier 0 0011 = current set point and dither amplitude set channel 25:24 channel number en 23 sets behavior of channel when the pin enable is low. 0 = channel turned off 1 = channel remains at last curren t set point. on/off 22 used when the channel is configured for on/off operation 0 = off 1 = on step size 21:12 dither step size (lsb value is 2 -4 of the curren t set point lsb) dither on/off 11 dither enable 0=disabled 1=enabled current setpoint 10:0 average current set point resolution = 0.78125 ma / bit when 0.2 ohm external resistor is used.
TLE7242-2G functional description and electrical characteristics data sheet 32 rev. 1.0, 2008-07-09 dither amplitude is the peak to peak amplitude of the dither waveform. note: the actual dither waveform is attenuated and phase shifted according to the frequency response of the control loop. dither steps is the number of pwm periods in ? of the dither waveform, set in spi message #4. rsense is the value of the external sense resistor response: current set point and dither amplitude set reset value: 00 00 00 00 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r/w msg_id ch1 ch0 en on/ off dither step size 1514131211109876543210 dither step size dither on/ off current set point field bits type description msg_id 30:26 message identifier 0 0011 = current set point and dither amplitude set channel 25:24 channel number en 23 sets behavior of channel wh en the pin enable is low. 0 = channel turned off 1 = channel remains at last current set point. on/off 22 used when the channel is configured for on/off operation 0 = off 1 = on step size 21:12 dither step size (lsb value is 2 -4 of the current set point lsb) dither on/off 11 dither enable 0=disabled 1=enabled current setpoint 10:0 average current set point resolution = 0.78125 ma / bit when 0.2 ohm external resistor is used. sense amplitude r s ditherstep size ditherstep mapp dither 320 2 * * 2 ] [ 15 ? = sense setpoint r setpoint ma current 320 2 ] [ 11 ? =
data sheet 33 rev. 1.0, 2008-07-09 TLE7242-2G functional description and electrical characteristics 5.6.2.5 spi message #4 - dither period set sent values: dither period set reset value: 00 00 00 00 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r/w msg_id ch1 ch0 unused 1514131211109876543210 not used dither steps field bits type description r/w 31 read / write bit 0 = read 1 = write msg_id 30:26 message identifier 0 0100 = dither period set channel 25:24 channel number dither steps 5:0 dither steps - # of dither steps in 1/4 of the dither waveform period. response: dither period set reset value: 00 00 00 00 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 msg_id ch1ch000000000 1514131211109876543210 0000000000 dither steps field bits type description msg_id 30:26 message identifier 0 0100 = dither period set channel 25:24 channel number dither steps 5:0 dither steps - # of dither steps in 1/4 of the dither waveform period. pwm period f s ditherstep dither * 4 [sec] =
TLE7242-2G functional description and electrical characteristics data sheet 34 rev. 1.0, 2008-07-09 5.6.2.6 spi message #5 - contro l variable set (kp and ki) sent values: control variable set (kp and ki) reset value: 00 80 08 00 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r/w msg_id ch1 ch0 kp 1514131211109876543210 kp ki field bits type description r/w 31 read / write bit 0 = read 1 = write msg_id 30:26 message identifier 0 0101 = control variable set (kp and ki) channel 25:24 channel number kp 23:12 kp - proportional coefficient ki 11:0 ki - integral coefficient response: control variable set (kp and ki) reset value: 00 80 08 00 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r/w msg_id ch1 ch0 kp 1514131211109876543210 kp ki field bits type description msg_id 30:26 message identifier 0 0101 = control variable set (kp and ki)t channel 25:24 channel number kp 23:12 kp - proportional coefficient ki 11:0 ki - integral coefficient
data sheet 35 rev. 1.0, 2008-07-09 TLE7242-2G functional description and electrical characteristics the duty cycle of the outx pin can be calculated from the difference equations: where error is the difference between the commanded average current and the measured average current in units of amps, where k indicates the integral number of pwm periods t hat have elapsed since current regulation was initiated. () () () ) 1 ( 1 * 28 . 1 ) ( ) ( 1 * 28 . 1 ? + ? ? ? = + ? ? ? = k int k error n rsense ki k int k int k error n rsense kp k dutycycle
TLE7242-2G functional description and electrical characteristics data sheet 36 rev. 1.0, 2008-07-09 5.6.2.7 spi message #6 - dy namic threshold value set sent values: dynamic threshold value set) reset value: 00 7f f4 00 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r/w msg_id ch1 ch0 unused transient mode threshold 1514131211109876543210 transient mode threshold integrator preload value field bits type description r/w 31 read / write bit 0 = read 1 = write msg_id 30:26 message identifier 0 0110 = dynamic threshold value set channel 25:24 channel number transient mode thresh 22:12 transient mode threshold setpoint changes grater than this threshold will activate the transient mode of operation. int. preload 11:0 integrator preload value this value will be loaded into the integrator when the controller transitions from transient mode to steady state mode. response: dynamic threshold value set reset value: 00 7f f4 00 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r/w msg_id ch1 ch0 0 transient mode threshold 1514131211109876543210 transient mode threshold integrator preload value field bits type description msg_id 30:26 message identifier 0 0110 = dynamic threshold value set channel 25:24 channel number
data sheet 37 rev. 1.0, 2008-07-09 TLE7242-2G functional description and electrical characteristics the preload value is limited to a maximum value of n * 2 17 transient mode thresh 22:12 transient mode threshold setpoint changes grater than this threshold will activate the transient mode of operation. int. preload 11:0 integrator preload value this value will be loaded into the integrator when the controller transitions from transient mo de to steady state mode. field bits type description sense threshold r ld odethresho transientm ma current 320 2 ] [ 11 ? = 8 2 ? ? = point set current value intpreload preload
TLE7242-2G functional description and electrical characteristics data sheet 38 rev. 1.0, 2008-07-09 5.6.2.8 spi message #7 - on/off co ntrol and fault mask configuration sent values: on/off control and fault mask configuration reset value: 00 00 00 00 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r/w msg_id unused cm0 cm1 cm2 cm3 fm0 fm1 fm2 fm3 1514131211109876543210 fmr fme diag_tmr az disable unused field bits type description r/w 31 read / write bit 0 = read 1 = write msg_id 30:26 message identifier 0 0111 = on/off control and fault mask configuration cmx 23, 22, 21, 20 control mode for channel #x 0 = current control 1 = on/off fmx 19, 18, 17, 16 fault mask for channel #x 0 = faults don?t trigger fault pin 1 = fault triggers fault pin fmr 15 fault mask for reset_b pin 0 = a low state on the enable pin does not activate the fault pin. 1 = a low state on the enable pin does activate the fault pin. note: when a high to low transition is detected on the enable pin, the enable fault will be latched un til the enable pin returns high and a diagnostic read message is received. fme 14 fault mast for enable pin 0 = a low state on the reset_b pin does not activate the fault pin. 1 = a low state on the reset_b pin does activate the fault pin. diag_tmr 13:12 diagnostic timer 00 = time_1 pre-divider = 128 01 = time_2 pre-divider = 192 10 = time_2 pre-divider = 192 11 = time_3 pre-divider = 256 az disable 11 auto-zero disable 0 = auto-zero enabled 1 = auto-zero disabled
data sheet 39 rev. 1.0, 2008-07-09 TLE7242-2G functional description and electrical characteristics response: on/off control and fault mask configuration reset value: 00 00 00 00 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r/w msg_id 0 0 cm0 cm1 cm2 cm3 fm0 fm1 fm2 fm3 1514131211109876543210 fmr fme diag_tmr az disable 00000000000 field bits type description msg_id 30:26 message identifier 0 0111 = on/off control and fault mask configuration cmx 23, 22, 21, 20 control mode for channel #x 0 = current control 1 = on/off fmx 19, 18, 17, 16 fault mask for channel #x 0 = faults don?t trigger fault pin 1 = fault triggers fault pin fmr 15 fault mask for reset_b pin 0 = a low state on the enable pin does not activate the fault pin. 1 = a low state on the enable pin does activate the fault pin. note: when a high to low transition is detected on the enable pin, the enable fault will be latched unt il the enable pin returns high and a diagnostic read message is received. fme 14 fault mask for enable pin 0 = a low state on the reset_b pi n does not activate the fault pin. 1 = a low state on the reset_b pin does activate the fault pin. diag_tmr 13:12 diagnostic timer 00 = time_1 pre-divider = 128 01 = time_2 pre-divider = 192 10 = time_2 pre-divider = 192 11 = time_3 pre-divider = 256 az disable 11 auto-zero disable 0 = auto-zero enabled 1 = auto-zero disabled
TLE7242-2G functional description and electrical characteristics data sheet 40 rev. 1.0, 2008-07-09 5.6.2.9 spi message #8 - diagnostic configuration sent values: diagnostic configuration reset value: xx ff ff ff h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r/w msg_id unused sb0 sb_retry0 sb1 1514131211109876543210 sb_retry1 sb2 sb_retry2 sb3 sb_retry3 field bits type description r/w 31 read / write bit 0 = read 1 = write msg_id 30:26 message identifier 0 1000= diagnostic configuration sbx 23:22 17:16 11:10 5:4 short to battery threshold 00 = 0.7 v 01 = 0.9 v 10 = 1.1 v 11 = 1.3 v sb_retryx 21:18 15:12 9:6 3:0 short to battery retry time retry after 4 * sb_retry * pwm periods response values: diagnostic configuration reset value: xx ff ff ff h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 msg_id 0 0 sb0 sb_retry0 sb1 1514131211109876543210 sb_retry1 sb2 sb_retry2 sb3 sb_retry3 field bits type description msg_id 30:26 message identifier 0 1000= diagnostic configuration
data sheet 41 rev. 1.0, 2008-07-09 TLE7242-2G functional description and electrical characteristics if the sb_retry field is programmed to the value 0, the s hort to battery retry period is identical to the programmed the pwm period as programmed in spi message #1. sbx 23:22 17:16 11:10 5:4 short to battery threshold 00 = 0.7 v 01 = 0.9 v 10 = 1.1 v 11 = 1.3 v sb_retryx 21:18 15:12 9:6 3:0 short to battery retry time retry after 4 * sb_retry * pwm periods field bits type description pwm x f sb_retry 4 period retry ? =
TLE7242-2G functional description and electrical characteristics data sheet 42 rev. 1.0, 2008-07-09 5.6.2.10 spi message #9 - diagnostic read sent values: diagnostic read reset value : xx 00 00 03h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r/w msg_id unused 1514131211109876543210 unused field bits type description r/w 31 read / write bit 0 = read 1 = write (interpreted as a read) msg_id 30:26 message identifier 0 1001 = diagnostic read response values: diagnostic read reset valu e: xx 00 00 03h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0msg_idsg0 off- tst0 sb0 sb- tst0 ol- off0 ol- on0 sg1 off- tst1 sb1 sb- tst1 1514131211109876543210 ol- off1 ol- on1 sg2 off- tst2 sb2 sb- tst2 ol- off2 ol- on2 sg3 off- tst3 sb3 sb- tst3 ol- off3 ol- on3 enl rbl field bits type description msg_id 30:26 message identifier 0 1001= diagnostic read (channel 0-3) sgx 25,19,13,7 short to ground - fault off-tstx 24,18,12,6 short to ground & open load (gate off) - tested sbx 23,17,11,5 short to battery - fault sb-tstx 22,16,10,4 short to battery - tested ol-offx 21,15,9,3 open load (gate off) - fault ol-onx 20,14,8,2 open load (gate on) - fault enl 1 enable pin latch rbl 0 reset_b pin latch
data sheet 43 rev. 1.0, 2008-07-09 TLE7242-2G functional description and electrical characteristics 5.6.2.11 spi message #10 - current read sent values: current read reset value: xx 00 00 00 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r/w msg_id ch1 ch0 unused 1514131211109876543210 unused field bits type description r/w 31 read / write bit 0 = read 1 = write (interpreted as a read) msg_id 30:26 message identifier 0 1010 = current read channel 25:24 channel number response values: current read reset value: xx 00 00 00 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 msg_id ch1ch000000000 1514131211109876543210 0 0 current read field bits type description msg_id 30:26 message identifier 0 1010 = current read channel 25:24 channel number current read 13:0 current read sense read r d currentrea ma current 320 2 ] [ 14 ? =
TLE7242-2G functional description and electrical characteristics data sheet 44 rev. 1.0, 2008-07-09 5.6.2.12 spi message #11 - autozero read sent values: autozero read reset value: xx 00 00 00 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r/w msg_id ch1 ch0 unused 1514131211109876543210 unused field bits type description r/w 31 read / write bit 0 = read 1 = write (interpreted as a read) msg_id 30:26 message identifier 0 1011 = autozero read channel 25:24 channel number response values: autozero read reset value: xx 00 00 00 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 msg_id ch1ch000000000 1514131211109876543210 ovl psl azon azoff autozero (on) value autozero (off) value field bits type description msg_id 30:26 message identifier 01011 = autozero read channel 25:24 channel number ovl 15 overvoltage latch this latch is set when the voltage on the bat pin exceeds the overvoltage threshold. the latch is reset when the bat pin voltage is below the threshold and the autozero read message is received.
data sheet 45 rev. 1.0, 2008-07-09 TLE7242-2G functional description and electrical characteristics psl 14 phase sync latch this latch is set when a rising edge occurs on the phase_sync pin. the latch is reset when the autozero read message is received. az on 13 autozero (on) occurred this latch is set when an autozero sequence has completed with a low common mode input voltage. the latch is reset when the autozero read message is received az off 12 autozero (off) occurred this latch is set when an autozero sequence has completed with a high common mode input voltage. the latch is reset when the autozero read message is received az (on) value 11:6 autozero (on) value the stored autozero value used when the pos and neg pin common mode voltage is low. az (off) value 5:0 autozero (off) value the stored autozero value used when the pos and neg pin common mode voltage is high field bits type description
TLE7242-2G functional description and electrical characteristics data sheet 46 rev. 1.0, 2008-07-09 5.6.2.13 spi message #12 - duty cycle read sent values: duty cycle read reset value: xx 00 00 00 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r/w msg_id ch1 ch0 unused 1514131211109876543210 unused field bits type description r/w 31 read / write bit 0 = read 1 = write (interpreted as a read) msg_id 30:26 message identifier 0 1100 = duty cycle read channel 25:24 channel number response values: autozero read reset value: xx 00 00 00 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 msg_id ch1ch000000 duty cycle 1514131211109876543210 duty cycle field bits type description msg_id 30:26 message identifier 0 1100 = duty cycle read channel 25:24 channel number duty cycle 18:0 duty cycle duty cycle of the pwm output of the selected channel. % 100 32 ? ? = n dutycycle cycle duty
data sheet 47 rev. 1.0, 2008-07-09 TLE7242-2G application information 6 application information note: the following information is given as a hint for the implementation of the device only and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the device. figure 18 application diagram note: this is a very simplified example of an application ci rcuit. the function must be verified in the real application. 6.1 further application information ? please contact us to get the pin fmea ? for further information you may contact http://www.infineon.com/ TLE7242-2G bat gnd_a enable v_signal si so sck neg0 out0 pos0 cs_b 10nf 10nf controller tc1766 (audo-ng) test 330 ? 10nf gnd_d fault clk 1k ? 0.2 ? spd15n06s2l-64 neg1 out1 pos1 10nf 1k ? 0.2 ? spd15n06s2l-64 neg2 out2 pos2 10nf 1k ? 0.2 ? spd15n06s2l-64 constant current solenoid neg3 out3 pos3 10nf 1k ? spd15n06s2l-64 on/off solenoid +3.3v or +5v ( c i/o voltage level) v5a 10nf v5d 100nf +5v digital phase_sync reset_b spi peripheral clock out i/o ports +5v analog 36v constant current solenoid constant current solenoid 10k ? 47uf v bat v bat v bat v bat v bat v bat v bat v bat power supply e.g. tle6368 100pf
TLE7242-2G package outlines data sheet 48 rev. 1.0, 2008-07-09 7 package outlines figure 19 pg-dso-28-26 green product (rohs-compliant) to meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. green products are rohs-compliant (i.e pb- free finish on leads and suitable for pb-fre e soldering according to ipc/jedec j-std-020). you can find all of our packages, so rts of packing and others in our infineon internet page ?products?: http://www.infineon.com/products . dimensions in mm
data sheet 49 rev. 1.0, 2008-07-09 TLE7242-2G revision history 8 revision history 0 version date changes 1.0 july 9, 2008 release of datasheet
edition 2008-07-09 published by infineon technologies ag 81726 munich, germany ? 2009 infineon technologies ag all rights reserved. legal disclaimer the information given in this docu ment shall in no event be regarded as a guarantee of conditions or characteristics. with respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, infine on technologies hereby disclaims any and all warranties and liabilities of any kind, including witho ut limitation, warranties of non-infrin gement of intellectua l property rights of any third party. information for further information on technology, delivery terms and conditions and prices, please contact the nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements, components may contain dangerous substances. for information on the types in question, please contact the nearest infineon technologies office. infineon technologies compon ents may be used in life-su pport devices or systems only with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safe ty or effectiveness of that de vice or system. life support devices or systems are intended to be implanted in the hu man body or to support an d/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

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